counter_4bit.v module counter_4bit ( input wire clk, // Clock input input wire rst_n, // Active-low reset input wire en, // Enable signal output r...
上升沿提取代码： reg [1:0] F1; always @(posedge clk) begin if(rst_n == 1\'b0) F1[1:0]<=2\'b00; else F1...
